1. Field of the Invention
This invention is related to the field of integrated circuits such as systems on a chip (SOCs) and, more particularly, to debug features of SOCs.
2. Description of the Related Art
As the number of transistors that can be integrated onto a single integrated circuit (IC) “chip” continues to increase, the amount of functionality and complexity that can be included increases as well. SOCs are one way in which the additional functionality/complexity is employed, by integrating various peripheral functionality onto the IC with one or more processors that are the central processing unit (CPU) of the system. The peripheral functionality can include processors as well (e.g. embedded processors, microcontrollers, digital signal processors, graphics processors, etc.), and can include fixed function circuitry such as peripheral interface controllers, encoders and decoders, graphics processing hardware, audio processing hardware, memory controllers, etc.
The continued integration of functionality/complexity into an SOC leads to complications for debugging. Both hardware problems and software problems can result in errant or unexpected operation, and typically the system engineer/software engineer needs to analyze various system state to identify the problem and how to fix it or work around it. CPUs generally include various debugging features (e.g. breakpoints on certain instructions or fetch addresses, address monitoring for data accesses, single step instruction execution modes, etc.). The CPU halt features, which are tied to the concept of a centralized, synchronous execution pipeline and execution of instructions, do not naturally extend to other components that have no notion of pipelining or instruction execution, and which run asynchronously with the CPUs and other blocks.